Improvements in semiconductor processes are making possible integrated circuits of increasing size and complexity. The semiconductor processing technologies that produce these integrated circuits have advanced to the point where complete systems, including memories, can now be reduced to a single integrated circuit or application specific integrated circuit (ASIC) device. These integrated circuits (also referred to as “die” or “chips”) may use many functions that previously could not be implemented on a single die. It is a common practice for the manufacturers of such integrated circuits to thoroughly test device functionality at the manufacturing site. However, due to the complex nature of today's integrated circuits and an attendant sensitivity to variations in manufacturing processes, manufacturers are constantly confronted with new testing challenges.
Before manufacturers release integrated circuits for shipment, the devices typically undergo a variety of testing procedures. In ASIC devices incorporating integrated memories, for example, specific tests are performed to verify that each of the memory cells within the integrated memory array(s) is functioning properly. This testing is necessary because perfect yields are difficult to achieve. It is not uncommon for a certain percentage of unpackaged ASIC die to contain memory cells which fail testing processes, due largely to non-systemic manufacturing defects. Such manufacturing issues are likely to increase as process geometries continue to shrink and the density of memory cells increases. Even today, up to 1 Gbits or more of dynamic random access memory (DRAM), static random access memory (SRAM) or flash memory can be integrated onto a single integrated circuit.
A number of ASIC memory testing strategies have evolved, many of which involve use of an external memory tester or Automated Test Equipment (ATE). If memory is accessible from input/output (I/O) pins, a hardware test mode can be utilized. In this mode, a production test system accesses the memory directly by writing to and reading from the memory bits. The main disadvantage of using such standard test modes is that the test system must test the devices interactively. Consequently, only a limited number of devices can be tested at a given time, and a significant amount of overhead time is incurred due to tester limitations (e.g., power up time is needed on certain pins while the mode is being accessed and while the tester is controlling the chip and checking the results).
If an embedded memory is embedded within an ASIC, built-in self-test (BIST) is often considered the most practical and efficient test methodology and is becoming increasingly popular with semiconductor vendors. BIST allows timely testing of the memory with a reasonably high degree of fault coverage, without requiring continual interactive control via external test equipment.
BIST refers in general to any test technique in which the testing algorithm or test vectors are generated internal to a discrete memory, an integrated circuit, or ASIC device. The testing algorithm used in BIST may be generally implemented in embedded circuitry of the device. Test vectors are sequences of signals that are applied to integrated circuitry to determine if the integrated circuitry is performing as designed. BIST can be used to test these memories located anywhere on the device.
In the BIST approach, a test pattern generator and test response analyzer are incorporated directly into the device to be tested. BIST operation is controlled by supplying an external clock and via use of a simple commencement protocol. BIST testing is typically distilled to the level of a “passed” or “failed” result. At the end of a typical structured BIST test, or “run”, a simple pass/fail signal is asserted, indicating whether the device passed or failed the test. Intermediate pass/fail signals may also be provided, allowing individual memory locations or group of locations to be analyzed. Unlike external testing approaches, at-speed testing with BIST is readily achieved. BIST also alleviates the need for long and convoluted test vectors and may function as a surrogate for functional testing or scan testing. Since the BIST structures exist and remain active throughout the life of the device, BIST can be employed at the board or system level to yield reduced system testing costs, reduce device rejects during production, and to reduce field diagnosis costs.
Many different types and styles of memory exist to store data for computers and similar type systems, wherein BIST circuits may be implemented. For example, random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), read only memory (ROM), programmable read only memory (PROM), electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash memory are all presently available to accommodate data storage. Each type of memory has its own particular advantages and disadvantages.
Flash memory, has become a popular type of memory because it combines the advantages of the high density and low cost of EPROM with the electrical erasability of EEPROM. Flash memory can be rewritten and can hold its contents without power, and thus is nonvolatile and is suitable for BIST circuitry and testing methods. Flash memory is used in many portable electronic products, such as cell phones, portable computers, voice recorders, etc. as well as in many larger electronic systems, such as cars, planes, industrial control systems, etc.
Individual memory cells are organized into individually addressable units or groups, which are accessed for read, program, or erase operations through address decoding circuitry. The individual memory cells are typically comprised of a semiconductor structure adapted for storing a bit of data and includes appropriate decoding and group selection circuitry, as well as circuitry to provide voltages to the cells being operated upon.
The erase, program, and read operations are commonly performed by application of appropriate voltages to certain terminals of the memory cell. In an erase or write operation the voltages are applied so as to cause a charge to be removed or stored in the memory cell. In a read operation, appropriate voltages are applied so as to cause a current to flow in the cell, wherein the amount of such current is indicative of the value of the data stored in the cell. The memory device includes appropriate circuitry to sense the resulting cell current in order to determine the data stored therein, which is then provided to data bus terminals of the device for access by other devices in a system in which the memory device is employed.
In a NOR configuration, the control gate is connected to a wordline associated with a row of memory cells to form sectors of such cells. In addition, the drain regions of the cells along a given column are connected together by a conductive bitline. Respective flash cells associated with a given bitline have stacked gate terminals coupled to a different wordline, while all the flash cells in the array generally have their source terminals coupled to a common source terminal. In operation, individual flash cells are addressed via the respective bitline and wordline using the peripheral decoder and control circuitry for programming (writing), reading or erasing functions.
Programming circuitry controls a bit of a cell by applying a signal to the wordline, which acts as a control gate, and changing bitline connections such that the bit is stored by the source and drain connections. Erasing is performed as a blanket operation wherein an array or sector of cells can be simultaneously erased. Generally, a gate voltage is applied to the control gates via the wordline(s) and a drain voltage is applied to the drains via the bitlines, while the sources may be configured to float.
In the blanket erasing of flash memory, cells within an array or sector are typically erased concurrently and can be accomplished by one or more applications of short erase pulses. After each erase pulse, an erase verification can be performed to determine if each cell in the array is now “erased” (blank), or yet remains “un-erased” or “under-erased”, (i.e., whether the cell has a threshold voltage above a predetermined limit). If an under-erased cell is detected, an additional erase pulse can be applied to the entire array. With such an erase procedure, however, cells that are sufficiently erased initially will also be repeatedly erased, leading to some cells becoming “over-erased” before other cells are sufficiently erased. A memory cell having a threshold voltage erased below a predetermined limit is commonly referred to as being over-erased. An over-erased condition is undesirable for many reasons.
In addition, testing algorithms used in BIST often attempt to determine a representative group of memory cells associated with a representative erase threshold level, by selecting edge columns, edge rows, or diagonal groupings of memory cells representative of the entire sector or array. Each grouping selection has a unique advantage, attempting to provide the representative erase level or a corresponding representative number of erase pulses required. Regardless of the grouping selected, however, a truly representative erase threshold level for the sector or array of memory cells is elusive, as differences exist between memory arrays and/or the particular ASIC application wherein the array resides. Further, the aforementioned grouping choices may not be sufficiently representative of the desired erase threshold level, and also may be difficult to implement in BIST circuitry.
In view of the foregoing, a need exists for an improved method implemented in BIST of erasing a sector or array of memory cells.